Field of the Invention
The present invention relates to a wiring board.
Description of Related Art
Wiring boards configured to allow semiconductor chips to be mounted are known (for example, refer to JP-A-2007-103648 and JP-A-2011-192692). On such wiring boards, a plurality of connection terminals configured to be connectable to the semiconductor chips are formed.
JP-A-2007-103648 describes that, in order to prevent electrical short circuit between the connection terminals due to a plating material, an insulating layer having a hole through which the plurality of connection terminals are exposed is formed, an insulating substance is formed between the plurality of connection terminals in the hole, and then the plurality of connection terminals are plated. JP-A-2011-192692 describes that, in order to prevent electrical short circuit between the connection terminals due to soldering, insulating layers formed between the connection terminals are thinned so as to be as thin as or thinner than the connection terminal.